Class-D Audio Amplifier
Description:
As we can see in diagram above, the analog signal, is injected in the input stage of amplifier that is an ADC. The sampled signal is outgoing to a microcontroller that encodes it in natural PWM. Therefore this PWM is sent to driver that drives a couple of MOS in half-bridge configuration. A Placement, on output before the loudspeakers, of an LC filter is needed.
The first block is an Texas Instruments's 16bits ADC that work in I2S (more suitable in audio field) in serial mode. The sample frequency is 44.1KHz, the clock must be provided externally by one of three allowed value (11.285 MHz in our case).
The microcontroller is a Microchip's DSPIC30F4013, it include DCI module dedicated to I2S encoding, five timer modules, DSP intructions, vectorized interrupts and UART module. As far as it's concern ADC's clock compatibity, as for DSPIC as for ADC we must use 11.285 MHz and by internal PLL we obtain (8x11.285) 90.3 MHz.
The driver IC is an Texas Intrument's UCC27200, it have very fast rise/fall time ( ~10nsec with load of 1000pF). The driver supply the correct signal sequence to the bridge for drive it and prevent the contemporany conduction of both MOS.
The MOS bridge is a Internation Rectifier's IR5852, the channel's resistivity si very low (only 0.09 Ohm) it mean that the dissipation power is low, the rise/fall time are very low (~ some nsec) that ensure that the minimum pulse can be reproduced, the input-gate capacitance are about 400pF.
The last stage is an second order LC filter.
For your consideration:
References:
[4] This project was designed and achieved in team with my colleague & friend eng. Luca Di Nuovo.