AC97-DCO

The project is the first release of a AC97 driver driven by a DCO (digital controlled oscillator).

The AC97 driver is used for drive an LM455, an audio cedec for PC systems which perform the analog intensive functions of AC97 Rev2.1 architecture. It provide 90dB of dinamic range using 18-bit Sigma-Delta A/D's and D/A's.

The DCO is used for provide to the driver the samples, therefore this samples are routed to LM4550 in approriate format.

schematic of design
schematic of design

DCO:

The DCO module is based on a simple 18bitsx1024 ROM addressed with 10bits address, and a ramp generator user controlled by external switchs.

The scope of dco is provide samples to driver and eventually (if user change the input word) change a frequency of signal.

The frequency change is obtained changing the slope of the ramp, and then taking minus samples of those that are located in the ROM cells.

AC97 DRIVER:

The AC97 driver is a LM4550 syncro-FSM (Finite State Machine) that get the samples from DCO, handle the command that are routed to LM4550, compose the serial frame to send , can manage the  LM input for use ADC's (not used in this project) and send tha data to LM4550.

SIMULATION:

In this section I show the simulation results.

As you can see in SDO push the values in the serial output data stream for LM4550.

Also the simulation is made simulating the input stimulus SDI (not used in the project r.1).

For your understanting I racommend you to read the LM4550 datasheet in which you can find the answer to almost all questions.

full view of simulation time space
full view of simulation time space
zoomed view of output data
zoomed view of output data

Results:

I think that the better way to show the results (out of simulation flow) is to show some oscilloscope screenshots, changing frequency of tone that I have put in the rom (500Hz tone).

ATLYS connected to oscilloscope
ATLYS connected to oscilloscope
47.04Hz sinusoidal signal
47.04Hz sinusoidal signal
93.63Hz sinusoidal signal
93.63Hz sinusoidal signal
187.9Hz sinusoidal signal
187.9Hz sinusoidal signal
375.9Hz sinusoidal signal
375.9Hz sinusoidal signal
757.5Hz sinusoidal signal
757.5Hz sinusoidal signal
1.5kHz sinusoidal signal (Note the scale's change from 5ms to 500usec)
1.5kHz sinusoidal signal (Note the scale's change from 5ms to 500usec)
3.01kHz sinusoidal signal
3.01kHz sinusoidal signal
6.02kHz sinusoidal signal
6.02kHz sinusoidal signal

Conclusion:

The first release of the design prove that implementation without external clock signal (using only the bit clock of LM4550) is possible but not very usefull (if you look the first sinusoid, and then all, the frequency is wrong (47Hz instead 470Hz we say).

This problem is due to the absence of a CMU (clock manager unit).

I think that in second release I use a system clock signal (ie 100MHz) for drive a sync-FSM.

References:

National Semiconductor LM4550 datasheet

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